1. Field of the Invention
The present invention relates to a non-volatile dynamic random access memory device; a page store device and a page recall device used in the same; a page store method using the page store device; and a page recall method using the page recall device.
2. Description of the Related Art
As for a non-volatile dynamic random access memory (NVDRAM) device, there are two kinds, i.e., a memory cell including a dynamic RAM (DRAM) cell and an electrically erasable programmable read only memory (EEPROM) cell and a memory cell having a ferroelectric.
An NVDRAM cell including a DRAM cell and an EEPROM cell has been described in the following:
(1) "A New Architecture for the NVDRAM--An EEPROM Backed-Up Dynamic RAM", IEEE Journal of Solid State Circuits, Vol. 23, No. 1, February 1988
(2) U.S. Pat. No. 4,611,309
(3) "A Versatile Stacked Storage Capacitor on a Flotox Cell for Megabit NVRAM Applications", from 1989 International Electron Devices Meeting Technical Digest, IEDM 89, pp. 595-598
(4) "A 256k-bit Non-Volatile PSRAM with Page Recall and Chip Store", 1991, Sym. VLSI circuit Dig. Tech. Papers, May, pp. 91-92
The advantage of these NVDRAMs is that while data may be quickly read from and written to the DRAM (volatile memory portion) during normal operation, it can be stored in the EEPROM (non-volatile memory portion) during power down.
An NVDRAM cell having a ferroelectric has been described in the following:
(1) "An Experimental 512-bit Nonvolatile Memory with a Ferroelectric Storage Cell" IEEE Journal of Solid State Circuits, Vol. 23, pp. 1171-1175, October, 1988.
(2) "A Ferroelectric DRAM Cell for High-Density NVRAM's", IEEE Electron Device Lett., Vol. 11, pp. 454-456, October, 1990
(3) "Present and Future Conditions of Ferroelectric Memory" Monthly, Semiconductor World, pp. 118-125 May, 1990
(4) "A 16 kb Ferroelectric Nonvolatile Memory with a Bit Parallel Architecture", ISSCC89, pp. 242-243 February, 1989,
In these NVDRAM memory devices with a memory cells having a ferroelectric, a capacitor, which has a thin film made of a ferroelectric with a crystal structure of a perovskite type, such as BST (BaSrTiO.sub.3 ), lead zirconate titanate (PZT), PLZT and PbTiO.sub.3 , is used in the memory cell. When an AC voltage is applied to the capacitor having a ferroelectric, the polarization state of the ferroelectric will have a hysteresis characteristic as shown in FIG. 18.
The operation in which data is written in an NVDRAM cell having a ferroelectric in a non-volatile manner will be described with reference to the hysteresis characteristic in FIG. 18.
When a positive electric field is applied to the capacitor in a point A (where the ferroelectric is not polarized), the polarization state of the retroelectric moves to a point B. When the electric field is removed under this condition, the polarization state moves to a point C, maintaining a positive residual polarization. Thereafter, when a negative electric field is applied to the capacitor, the ferroelectric is depolarized. Further application of a negative electric field inverts the polarization state of the ferroelectric and moves it to a point D. When the electric field is removed under this condition, the polarization state moves to a point E, maintaining a negative residual polarization. Accordingly, data can be stored in the NVDRAM in a non-volatile manner by inverting the polarization of the ferroelectric and maintaining a positive or negative residual polarization. In the case where a positive electric field is applied to and removed from the capacitor, the polarization state of the ferroelectric in the capacitor moves between the points B and C, and in the case where a negative electric field is applied to and removed from the capacitor, the polarization state of the ferroelectric moves between the points D and E. The polarization is not inverted between the points B and C or between the points D and E. Thus, data can be stored in the NVDRAM cell having a ferroelectric in a volatile manner in the same way as in a conventional DRAM cell.
In these NVDRAM memory devices having a memory cell with a ferroelectric, the number of elements constituting a memory cell can be decreased, compared with the combination of a DRAM cell and an EEPROM cell. Therefore, the area of the memory cell is decreased, making it possible to achieve high integration.
Here, an NVDRAM memory device with a ferroelectric cell using two transistors per cell will be described. As shown in FIG. 19, such an NVDRAM memory device includes a plurality of word lines WL and plate lines PT corresponding thereto. The word lines WL are connected to a word line decoder 1, and the plate lines PT are connected to a plate line decoder 2. The NVDRAM memory device further includes a plurality of pairs of bit lines bit and bit, and the respective pair of bit lines bit and bit is connected to a sense amplifier 3. In FIG. 19, one exemplary set of sense amplifier 3 and one pair of bit lines bit and bit connected thereto is shown.
Each intersection where the word line WL and the plate line PT corresponding thereto cross the bit lines bit and bit constitutes a memory cell 4. In FIG. 19, only one exemplary memory cell 4 is shown. The memory cell 4 includes Two capacitors C1 and C2 and two selecting transistors Q1 and Q2. One terminal of the capacitor C1 and that of the capacitor C2 are connected to the bit lines bit and bit through the selecting transistors Q1 and Q2, respectively. The other one terminal of the capacitor C1 and that of the capacitor C2 are connected to the plate line PL. Respective gates of the selecting transistors Q1 and Q2 are connected to the word line WL.
In the NVDRAM memory device having the above-mentioned structure, the word line decoder 1 selects one word line WL and the plate line decoder 2 selects one plate line PT, based on an address input into an address buffer 5. The memory cell 4 is accessed in a selected mode based on a control signal input into a control signal input buffer 6. That is, in a DRAM mode where volatile data is accessed, an access operation is controlled by a DRAM mode timing control circuit 7; in a recall mode where non-volatile data is read, an access operation is controlled by a recall mode timing control circuit 8; and in a store mode where non-volatile data is written, an access operation is controlled by a store mode timing control circuit 9. Data to be accessed is transmitted from an external device to the NVDRAM memory device or transmitted from the NVDRAM memory device to the external device through an I/O interface.
The data write operation in the store mode by the store mode timing control circuit 9 will be described in detail with reference to FIGS. 20A and 20B.
In the case where data "0" is written, as shown in FIG. 20A, a voltage signal of 0 V is applied to the bit line bit and a voltage signal of 5 V is applied to the bit line bit, whereby the word line WL is activated. Under this condition, a pulse voltage signal changing from 0 V to 5 V to 0 V is applied to the plate line PT. A ferroelectric of the capacitor C1 has its polarization state changed from the point C or the point E to the point B and then to the point C; and a ferroelectric of the capacitor C2 has its polarization state changed from the point D to the point E and then to the point D (see FIG. 18). Thus, even though an electric field is removed from the capacitors C1 and C2 thereafter, the ferroelectrics of the capacitors C1 anti C2 maintain the residual polarizations thereof at the points C and E, respectively. In this way, data "0" is stored in a non-volatile manner. In the case where data "1" is written, as shown in FIG. 20B, a voltage of 5 V is applied to the bit line bit and a voltage of 0 V is applied to the bit line bit, whereby the word line WL is activated. Under this condition, a pulse voltage signal changing from 0 V to 5 V to 0 V is applied to the plate line PT. The ferroelectrics of the capacitors C1 and C2 maintain the residual polarizations thereof at the points E and C, respectively. In this way, data "1" is stored in a non-volatile manner.
Next, the data read operation in the recall mode by the recall mode timing control circuit 8 will be described in detail with reference to FIG. 20C.
The bit lines bit and bit are precharged to 0 V and made to be in a floating state. Then the word line WL is activated. Under this condition, a pulse voltage signal changing from 0 V to 5 V is applied to the plate line PT. In the case where data "0" is stored, the polarization state of the ferroelectric of the capacitor C1 is changed from the point C to the point B; and the polarization state of the ferroelectric of the capacitor C2 is changed from the point E to the point B (see FIG. 18). In this case, the ferroelectric of the capacitor C2 has its polarization state inverted. Therefore, the electric potential of the bit line bit connected to the capacitor C2 becomes about hundreds of milli-volts higher than that of the bit line bit. The sense amplifier 3 detects the difference in electric potential between the bit lines bit and bit and the non-volatile data can be read out. In this case, the polarization states of the ferroelectrics of the capacitors C1 and C2 move to the point B, so that data has been stored in a non-volatile manner is lost (i.e., destructive read is performed).
The difference in electric potential between the bit lines bit and bit in the recall mode is directly proportional to the residual polarization and is inversely proportional to the bit line capacitance. Thus, as the residual polarization is larger and the bit line capacitance is smaller, the difference in electric potential is larger, so that difference in electric potential can be easily detected by the sense amplifier 3.
The access operation in the DRAM mode controlled by the DRAM mode timing control circuit 7 is performed under the condition that the plate line PT is applied with a voltage of 0 V, in the same way as in a conventional DRAM memory device. The polarization state of the ferroelectrics of the capacitors C1 and C2 move only between the points D and E (see FIG. 18). In the same way as in a conventional DRAM memory device, data can be stored in a volatile manner and read out from the memory cell by means of an electric charge stored in the capacitors C1 and C2.
The NVDRAM memory device having a memory cell with a ferroelectric can also be operated only in the store mode and in the recall mode. However, the ferroelectrics in the capacitors C1 and C2 of the memory cell 4 have a limited possible number of polarization inversions so that the recall/store operation is limited to about 10.sup.9 to 10.sup.12 times. If an access operation is successively performed in a cycle of about 100 ns, the memory cell 4 is worn out in a few days.
In order to prevent the above-mentioned disadvantage, in the NVDRAM memory device having a memory cell with a ferroelectric, the data is accessed during normal read/write operations in the DRAM mode, where the polarization of the ferroelectric is not inverted. Only in the case where data should be stored in a non-volatile manner (i.e., at a time when a power source is turned ON or OFF), data is accessed in the recall mode and in the store mode. In this way, the number of data access involving the polarization inversion is made as small as possible. A cell area of the NVDRAM cell including two Transistors and two capacitors is large, which makes it difficult to highly integrate cells. In view of this, an NVDRAM cell including one transistor and one capacitor, using a dummy cell, has been suggested.
The conventional NVDRAM memory devices have the following problems:
In the conventional NVDRAM memory cell, a recall operation or a store operation is performed in accordance with an address input into an external address pad or an address generated by an internal address counter circuit. According to this method, if access operations in the recall mode or the store mode are repeatedly ordered due to the bugs in a program or the runaway of a computer device controlling these operations, the polarization is also repeatedly inverted. As a result, the number of data access will reached the limited access number and make the life of the memory cell 4 much shorter than that expected.
Data access operation in the recall mode in the conventional NVDRAM cell is a destructive read of data, as described above. Therefore, if data which is once read out is somehow lost, this data cannot be restored any more.
When an electric charge as volatile data is stored in the capacitor during the data access operation in the recall mode, this electric charge causes a noise to disturb the read out of non-volatile data.
When a memory cell has a one transistor per cell structure as in the conventional NVDRAM memory device, a dummy cell provided for the normal memory cell with one capacitor cannot be formed in the same configuration as that of the normal memory cell. This causes the production of a semiconductor memory device to be complicated.
In the conventional NVDRAM memory devices, in some cases, recorded data is broken, if the store operation is performed immediately after a power source is turned ON.
In the conventional NVDRAM memory device, data is stored as a variable electric charge in a capacitor of each memory cell, since the memory cells have no built-in restore capability. Each memory cell has no active pull-up or pull-down circuit elements for altering the electric charge in the capacitor of each memory cell independently. Therefore, a sense amplifier as an external circuit should be used to provide an electric charge corresponding to a full swing logic 0 or logic 1 onto the capacitor of the memory cell.
Lacking an externally initiated restore operation following data recall from an EEPROM cell portion with polarization inversion to a DRAM cell portion without polarization in the conventional NVDRAM cell, the memory cell will contain degraded voltage levels of logic state 0 or 1. When the data in the DRAM cells are subsequently read out in a conventional DRAM manner, these degraded voltage levels in memory cells may result in the detection of incorrect data. Therefore, it is necessary to perform a conventional DRAM restore operation during the recall/store operation to ensure the voltage level of full logic state 0 or 1 in the DRAM cell. This restore operation can only reliably perform to one memory cell per bit line at any one time.
Thus, in the NVDRAM memory device having a memory cell with a ferroelectric, recall/store operation for all memory cells is not feasible simultaneously; only one memory cell per bit line should be recalled or stored at any one time.
For the above reason, in an apparatus having a plurality of NVDRAM memory devices, for example, the number of the store operations performed to store data in all memory cells is represented by (Number of NVDRAM memory devices).times.(Number of word lines). Assuming all memory cells connected to one word line is defined as one page, the number of the store operation is represented by (Number of NVDRAM memory devices).times.(Number of pages). When the NVDRAM memory devices are increased in number, the store operation is repeated in accordance with the number of the NVDRAM memory devices, resulting in the -waste of time. In the case where the store operation is repeated for more than the above-mentioned times due to the bugs in a program or the runaway of an external control circuit, the polarization inversion of the ferroelectric is repeated in a wasteful manner.
A page recall device and a page recall method using the same as shown in FIG. 21 is described by Eby et al., in U.S. Pat. No. 5,146,431 (the inventor of the present invention is a coinventor of this patent). The recall operation has the same problems as those of the store operation described above. In the recall device shown in FIG. 21, in the case where the recall operation is repeated for more than required number due to the runaway of the external control circuit, etc. the polarization inversion of the ferroelectric is repeated in a wasteful manner.